This application claims benefit of priority under 35USC xc2xa7119 to Japanese Patent Application No. 1999-347645, filed on Jan. 7, 1999, and No. 2000-354677, filed on Nov. 21, 2000, the entire contents of which are incorporated by reference herein.
The present invention relates to a semiconductor storage device and, more particularly, to a semiconductor storage device including a circuit for calculating addresses.
FIG. 10 shows the arrangement of an address calculation circuit and cache cell array included in a cache memory mounted in a microprocessor or the like as a semiconductor storage device related to the present invention.
An instruction code executed by a microprocessor (not shown) contains an immediate value and register file value, i.e., a register number for designating a base address. This immediate value and base address are added by an adder ADD to generate an index address.
The index address is supplied to an address decoder AD to be decoded. One of a plurality of word lines WL is selected on the basis of the decoding result. The word lines WL run in the row direction of a cache cell array CCA having an array of memory cells to commonly connect the memory cells arranged in the row direction. One of the word lines is selected on the basis of an immediate value and base address.
Consider a case wherein 16 word lines WL0 to WL15 are accessed by a 4-bit address. If an immediate value is xe2x80x9c0000xe2x80x9d and a base address is xe2x80x9c0001xe2x80x9d, the output from the adder ADD becomes xe2x80x9c0001xe2x80x9d. This output is supplied to the address decoder AD, and xe2x80x9c0000000000000010xe2x80x9d is output to the 16 word lines WL. Of bits 0 to 15, xe2x80x9c1xe2x80x9d is assigned to only the first bit, and xe2x80x9c0xe2x80x9ds are assigned to the remaining bits, thereby selecting the word line WL1 corresponding to the first bit.
The following problem arises in an address calculation circuit included in this semiconductor storage device. An immediate value and base address are not input to the adder ADD at the same timing, but the base address is input at a later thing for the following reason. The immediate value is directly contained in the instruction code, whereas only the register number of the base address is contained in the instruction code itself, and it takes time to determine the value of the base address and output it after the register number is input to the register file. For this reason, no output can be obtained from the adder ADD until the value of the base address is determined, and it takes time to select a word line WL, resulting in a decrease in overall access speed.
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor storage device which can increase the access speed.
A semiconductor storage device according to the present invention is a device in which access is made by generating an address by using first and second signals and characterized by comprising an address decoder for generating a decode signal by performing decoding using the first signal whose value is determined at a timing equal to or earlier than a timing at which a value of the second signal is determined, a word line rotator for rotating the decode signal generated by the address decoder by using the second signal to generate a word line selection signal, and a cell array to which the word line selection signal generated by the word line rotator is supplied to select a word line.
In addition, according to the present invention, there is provided a semiconductor storage device in which access is made by generating an address by using first and second signals, characterized by comprising an address decoder for generating a decode signal by performing decoding using a predetermined pit of the first signal whose value is determined at a timing equal to or earlier than a timing at which a value of the second signal is determined, a word line rotator for rotating the decode signal generated by the address decoder by using a predetermined bit of the second signal to generate a word line selection signal, an adder for generating a carry signal representing the presence/absence of a carry by performing addition processing using bits of the first signal excluding the predetermined bit and bits of the second signal excluding the predetermined bit, a carry rotator for generating a second word line selection signal by rotating the first word line selection signal, generated by the word line rotator, in accordance with the carry signal generated by the adder, as needed, and a cell array to which the second word line selection signal generated by the carry rotator is supplied to select a word line.
Furthermore, according to the present invention, there is provided a semiconductor storage device in which access is made by generating an address by using first and second signals, characterized by comprising an address decoder for generating a decode signal by performing decoding using data of Q bits of data of N bits of the first signal whose value is determined at a timing equal to or earlier than a timing at which a value of the second signal is determined, excluding data of upper M bits, and data of lower P bits contained in the data of the N bits, a word line rotator for rotating the decode signal generated by the address decoder by using data of Q bits contained in data of N bits of the second signal to generate a first word line selection signal, an adder for generating a carry signal representing the presence/absence of a carry at a position of the Pth bit by performing addition processing using the data of the N bits of the first signal and the data of the N bits of the second signal, and also outputting an addition result at a position of the Nth bit, a carry rotator for generating a second word line selection signal by rotating the first word line selection signal, generated by the word line rotator, in accordance with the carry signal generated by the adder, as needed, and a cell array to which the second word line selection signal generated by the carry rotator is supplied to select a word line and output R data, and a multiplexer to which the addition result at the position of the Mth bit is supplied to select and output one of the R data.
In this case, the word line rotator may include a multiplexer group having series-connected multiplexers equal in number of bit signals for the second signal.
In addition, a signal, of the second signals supplied to the word line rotator, whose value is determined at a latest timing may be supplied to the last multiplexer of the multiplexer group.
The carry rotator can be placed between the word line rotator and the memory cell array.
As described above, according to the semiconductor storage device of the present invention, decoding processing is performed by using first the first signal whose value is determined at an earlier timing, and then rotation is performed by using the second signal whose vale is determined at a later timing. This makes it possible to shorten a path through which the second signal whose value is determined at a later timing passes through, i.e., a critical path, and increase the overall access speed.